Cadence Tensilica IP Powers Analog Devices’ Next-Generation DSP Architecture
Cadence today announced that its Tensilica IP Group and Analog Devices, Inc. (ADI) worked together to develop the latest generation of SHARC... Read More
Cadence Subsystem for PCIe 6.0 Architecture Achieves First-Pass PCI Express Specification Compliance
Cadence today announced that its PHY and controller IP for the PCI Express (PCIe) 6.0 specification, implemented in the TSMC N3 process, achieved... Read More